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? semiconductor components industries, llc, 2010 june, 2010 ? rev. 7 1 publication order number: mc33363a/d mc33363a high voltage switching regulator the mc33363a is a monolithic high voltage switching regulator that is specifically designed to operate from a rectified 240 vac line source. this integrated circuit features an on ? chip 700 v / 1.5 a sensefet power switch, 500 v active off ? line startup fet, duty cycle controlled oscillator, current limiting comparator with a programmable threshold and leading edge blanking, latching pulse width modulator for double pulse suppression, high gain error amplifier, and a trimmed internal bandgap reference. protective features include cycle ? by ? cycle current limiting, input undervoltage lockout with hysteresis, output overvoltage protection, and thermal shutdown. this device is available in a 16 ? lead dual ? in ? line and wide body surface mount packages. features ? enhanced power capability over mc33363 ? on ? chip 700 v, 1.5 a sensefet power switch ? rectified 240 vac line source operation ? on ? chip 500 v active off ? line startup fet ? latching pwm for double pulse suppression ? cycle ? by ? cycle current limiting ? input undervoltage lockout with hysteresis ? output overvoltage protection comparator ? trimmed internal bandgap reference ? internal thermal shutdown ? these are pb ? free devices* figure 1. simplified application this device contains 221 active transistors. startup reg osc thermal leb pwm dc output startup input gnd 4, 5, 12, 13 mirror 7 ac input regulator output 6 8 c t r t pwm latch ea i pk v cc 3 11 16 9 10 1 compensation voltage feedback input power switch drain overvoltage protection input driver ovp uvlo s r q marking diagrams a = assembly location wl = wafer lot yy = year ww = work week g = pb ? free package 1 16 pdip ? 16 p suffix case 648e 1 16 so ? 16w dw suffix case 751n 116 13 12 11 10 9 3 4 5 6 7 8 (top view) startup input v cc gnd r t c t regulator output power switch drain gnd compensation pin connections overvoltage protection input voltage feedback input mc33363ap awlyywwg mc33363adw awlyywwg http://onsemi.com see detailed ordering and shipping information in the package dimensions section on p age 7 of this data sheet. ordering information *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d.
mc33363a http://onsemi.com 2 maximum ratings (note 1) rating symbol value unit power switch (pin 16) drain voltage drain current ? 1.0 to v reg ? p suffix, dual ? in ? line case 648e thermal resistance, junction ? to ? air thermal resistance, junction ? to ? case (pins 4, 5, 12, 13) ja r jc c/w ? to ? air thermal resistance, junction ? to ? case (pins 4, 5, 12, 13) refer to figures 17 and 18 for additional thermal information. ja r jc ? 25 to +150 c ? 55 to +150 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. this device series contains esd protection and exceeds the following tests: human body model 2000 v per mil ? std ? 883, method 3015. machine model method 150 v. electrical characteristics (v cc = 20 v, r t = 10 k, c t = 390 pf, c pin8 = 1.0 f, for typical values t j = 25 c, for min/max values t j is the operating junction temperature range that applies (note 2), unless otherwise noted) characteristic symbol min typ max unit (pin 8) c) ? 30 ? 44 ? 8.0 oscillator (pin 7) c (v cc = 20 v) t j = t low to t high (v cc = 20 v to 40 v) c t = 2.0 nf t j = 25 c (v cc = 20 v) t j = t low to t high (v cc = 20 v to 40 v) ? 67.5 ? 310 315 75 76 f osc / v ? 0.1 error amplifier (pins 9, 10) c) ? 0.6 ? 20 c) ? 82 ? db 2. tested junction temperature range for the mc33363a: t low = ? 25 ct high = +125 c
mc33363a http://onsemi.com 3 electrical characteristics (v cc = 20 v, r t = 10 k, c t = 390 pf, c pin8 = 1.0 f, for typical values t j = 25 c, for min/max values t j is the operating junction temperature range that applies (note 2), unless otherwise noted) characteristic unit max typ min symbol (pins 9, 10) c) ? 1.0 ? mhz a, v fb < 2.0 v) low state (i sink = 100 a, v fb > 3.0 v) ? 5.3 0.2 ? 0.35 overvoltage detection (pin 11) ? 100 pwm comparator (pins 7, 9) ? 50 0 power switch (pin 16) ? source on ? state resistance (i d = 200 ma) t j = 25 c t j = t low to t high ? ? 7.5 ? 9.0 20 drain ? source off ? state leakage current (v ds = 650 v) t j = 25 c t j = t low to t high ? ? 0.25 ? 1.0 50 a ? 50 ? ns ? 50 ? ns overcurrent comparator (pin 16) startup control (pin 1) ? 25 c to 100 c) v cc = 0 v v cc = (v th(on) ? 0.2 v) ? state leakage current (v in = 50 v, v cc = 20 v) ? 40 a undervoltage lockout (pin 3) ? on total device (pin 3) ? ? 0.27 3.4 ? 25 ct high = +125 c
mc33363a http://onsemi.com 4 7.0 1.0 m f osc , oscillator frequency (hz) figure 2. oscillator frequency versus timing resistor r t , timing resistor (k ) figure 3. power switch peak drain current versus timing resistor 500 k 200 k 100 k 50 k 20 k 10 k 10 15 20 30 50 v cc = 20 v t a = 25 c c t = 100 pf c t = 200 pf c t = 500 pf c t = 1.0 nf c t = 2.0 nf c t = 5.0 nf c t = 10 nf 70 v cc = 20 v c t = 1.0 f t a = 25 c inductor supply voltage and inductance value are adjusted so that i pk turn-off is achieved at 5.0 s. r t , timing resistor (k ) 1.5 i pk , power switch peak drain current (a ) 0.8 0.6 0.4 0.2 0.15 7.0 10 15 20 30 40 70 50 0.3 1.0 0 0 1.0 70 10 100 7.0 0.8 v sat , output saturation voltage (v) i o , output load current (ma) d max , maximum output duty cycle (%) timing resistor ratio a vol , open loop voltage gain (db) f, frequency (hz) i chg , oscillator figure 4. oscillator charge/discharge current versus timing resistor r t , timing resistor (k ) figure 5. maximum output duty cycle versus timing resistor ratio figure 6. error amp open loop gain and phase versus frequency figure 7. error amp output saturation voltage versus load current /i dscg charge/discharge current (ma) , excess phase (degrees) 0.5 0.3 0.2 0.15 0.1 0.08 80 60 40 20 0 -20 60 50 40 30 -1.0 -2.0 2.0 1.0 0 10 15 20 30 70 2.0 3.0 5.0 7.0 10 100 1.0 k 10 k 100 k 1.0 m 10 m 0.2 0.4 0.6 0.8 1.0 0 30 60 90 120 150 180 r d /r t ratio discharge resistor pin 7 to gnd v cc = 20 v c t = 2.0 nf t a = 25 c r c /r t ratio charge resistor pin 7 to v reg v cc = 20 v v o = 1.0 to 4.0 v r l = 5.0 m c l = 2.0 pf t a = 25 c gain phase v cc = 20 v t a = 25 c source saturation (load to ground) sink saturation (load to v ref ) v cc = 20 v t a = 25 c gnd v ref 50
mc33363a http://onsemi.com 5 1.80 v 0.5 v/div 1.0 s/div 20 mv/div 1.0 s/div v cc = 20 v a v = -1.0 c l = 10 pf t a = 25 c figure 8. error amplifier small signal transient response figure 9. error amplifier large signal transient response v cc = 20 v a v = -1.0 c l = 10 pf t a = 25 c 1.75 v 1.70 v 3.00 v 1.75 v 0.50 v 0 0 v reg , regulator voltage change (mv) figure 10. regulator output voltage change versus source current i reg , regulator source current (ma) figure 11. peak startup current versus power supply voltage v cc = 20 v r t = 10 k t a = 25 c -20 -40 -60 -80 4.0 8.0 12 16 20 0 1 2 3 4 5 6 7 8 02468101214 0 1 2 3 4 5 6 7 8 0 1020304050 figure 12. peak startup current versus startup input voltage v pin1 , startup pin voltage (v) i start , startup current (ma) v cc , supply voltage (v) i start , startup current (ma) v cc = 0 v t a = 25 c v cc = 14 v t a = 25 c v pin1 = 50 v t a = 25 c
mc33363a http://onsemi.com 6 1.0 160 -50 32 c oss , drain-source capacitance (pf) v ds , drain-source voltage (v) v cc = 20 v t a = 25 c r ds(on) , drain-source on-resistance ( ) t a , ambient temperature ( c) i d = 200 ma figure 13. power switch drain ? source on ? resistance versus temperature figure 14. power switch drain ? source capacitance versus voltage pulse tested at 5.0 ms with < 1.0% duty cycle so that t j is as close to t a as possible. c oss measured at 1.0 mhz with 50 mvpp. 24 16 8.0 0 120 40 80 0 -25 0 25 50 75 150 100 10 100 1000 125 4.0 0 3.6 i cc , supply current (ma) v cc , supply voltage (v) figure 15. supply current versus supply voltage r t = 10 k pin 1 = open pin 4, 5, 10, 11, 12, 13 = gnd t a = 25 c 2.4 1.6 0.8 0 10 20 30 40 0.01 100 r ja , thermal resistance t, time (s) figure 16. dw and p suffix transient thermal resistance junction-to-air ( c/w) 0.1 1.0 10 100 10 1.0 l = 12.7 mm of 2.0 oz. copper. refer to figures 17 and 18. 3.2 c t = 2.0 nf c t = 390 pf 0 100 r ja , thermal resistance l, length of copper (mm) p d(max) for t a = 50 c figure 17. dw suffix (sop ? 16l) thermal resistance and maximum power dissipation versus p.c.b. copper length junction-to-air ( c/w) p d , maximum power dissipation (w) r ja 90 70 60 80 50 10 20 30 40 50 2.8 2.4 1.6 1.2 2.0 0.8 0.4 0 40 30 0 0 figure 18. p suffix (dip ? 16) thermal resistance and maximum power dissipation versus p.c.b. copper length ?? ?? graphs represent symmetrical layout 3.0 mm printed circuit board heatsink example l l 100 80 60 40 20 10 20 30 40 50 l, length of copper (mm) p d , maximum power dissipation (w) 5.0 4.0 3.0 2.0 1.0 0 p d(max) for t a = 70 c 2.0 oz copper ??? ??? ja r , thermal resistance ja junction-to-air ( c/w) ??? ??? graphs represent symmetrical layout 3.0 mm l l 2.0 oz copper ?? ??
mc33363a http://onsemi.com 7 pin function description pin function description 1 ? this pin has been omitted for increased spacing between the rectified ac line voltage on pin 1 and the v cc potential on pin 3. f for stability. ? these pins have been omitted for increased spacing between the high voltages present on the power switch drain, and the ground potential on pins 12 and 13. ordering information device package shipping ? mc33363adwg soic ? 16wb (pb ? free) 47 units / rail mc33363adwr2g soic ? 16wb (pb ? free) 1000 / tape & reel MC33363APG pdip ? 16 (pb ? free) 25 units / rail ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
mc33363a http://onsemi.com 8 figure 19. representative block diagram oscillator pwm pwm latch current limit thermal shutdown error startup control band gap regulator uvlo 14.5 v/ 9.5 v ovp 2.6 v current 2.6 v regulator output 6.5 v r c 8 6 7 4, 5, 12, 13 gnd 11 16 9 10 1 voltage compensation power switch overvoltage ac input dc 2.25 i i 6.0 r s q driver 3 startup input 450 t t comparator leading edge blanking mirror 4 i 270 a v cc comparator protection input drain feedback input amplifier output figure 20. timing diagram capacitor c compensation pwm comparator output oscillator output pwm latch q output power switch gate drive leading edge blanking input (power switch drain current) normal pwm operating range output overload current limit threshold 0.6 v 2.6 v current limit propagation delay t
mc33363a http://onsemi.com 9 operating description introduction the mc33363a represents a new higher level of integration by providing all the active high voltage power, control, and protection circuitry required for implementation of a flyback or forward converter on a single monolithic chip. this device is designed for direct operation from a rectified 240 vac line source and requires a minimum number of external components to implement a complete converter. a description of each of the functional blocks is given below, and the representative block and timing diagrams are shown in figures 19 and 20. oscillator and current mirror the oscillator frequency is controlled by the values selected for the timing components r t and c t . resistor r t programs the oscillator charge/discharge current via the current mirror 4 i output, figure 4. capacitor c t is charged and discharged by an equal magnitude internal current source and sink. this generates a symmetrical 50% duty cycle waveform at pin 7, with a peak and valley threshold of 2.6 v and 0.6 v respectively. during the discharge of c t , the oscillator generates an internal blanking pulse that holds the inverting input of the and gate driver high. this causes the power switch gate drive to be held in a low state, thus producing a well controlled amount of output deadtime. the amount of deadtime is relatively constant with respect to the oscillator frequency when operating below 1.0 mhz. the maximum power switch duty cycle at pin 16 can be modified from the internal 50% limit by providing an additional charge or discharge current path to c t , figure 21. in order to increase the maximum duty cycle, a discharge current resistor r d is connected from pin 7 to ground. to decrease the maximum duty cycle, a charge current resistor r c is connected from pin 7 to the regulator output. figure 5 shows an obtainable range of maximum output duty cycle versus the ratio of either r c or r d with respect to r t . figure 21. maximum duty cycle modification pwm current regulator output 1.0 r c 8 6 2.25 i i t t mirror 4 i oscillator comparator r d r c 7 current limit reference blanking pulse the formula for the charge/discharge current along with the oscillator frequency are given below. the frequency formula is a first order approximation and is accurate for c t values greater than 500 pf. for smaller values of c t , refer to figure 2. note that resistor r t also programs the current limit comparator threshold. i chg dscg 5.4 r t f i chg dscg 4c t pwm comparator and latch the pulse width modulator consists of a comparator with the oscillator ramp voltage applied to the non ? inverting input, while the error amplifier output is applied into the inverting input. the oscillator applies a set pulse to the pwm latch while c t is discharging, and upon reaching the valley voltage, power switch conduction is initiated. when c t charges to a voltage that exceeds the error amplifier output, the pwm latch is reset, thus terminating power switch conduction for the duration of the oscillator ramp ? up period. this pwm comparator/latch combination prevents multiple output pulses during a given oscillator clock cycle. the timing diagram shown in figure 20 illustrates the power switch duty cycle behavior versus the compensation voltage. current limit comparator and power switch the mc33363a uses cycle ? by ? cycle current limiting as a means of protecting the output switch transistor from overstress. each on ? cycle is treated as a separate situation. current limiting is implemented by monitoring the output switch current buildup during conduction, and upon sensing an overcurrent condition, immediately turning off the switch for the duration of the oscillator ramp ? up period. the power switch is constructed as a sensefet allowing a virtually lossless method of monitoring the drain current. it consists of a total of 2819 cells, of which 65 are connected to a 6.0 ground ? referenced sense resistor. the current sense comparator detects if the voltage across the sense resistor exceeds the reference level that is present at the inverting input. if exceeded, the comparator quickly resets the pwm latch, thus protecting the power switch. the current limit reference level is generated by the 2.25 i output of the current mirror. this cu rrent causes a reference voltage to appear across the 450 resistor. this voltage level, as well as the oscillator charge/discharge current are both set by resistor r t . therefore when selecting the values for r t and c t , r t must be chosen first to set the power switch peak drain current, while c t is chosen second to set the desired oscillator frequency. a graph of the power switch peak drain current versus r t is shown in figure 3 with the related formula below. i pk 15.95 r t 1000 ? 1.14 the power switch is designed to directly drive the converter transformer and is capable of switching a
mc33363a http://onsemi.com 10 maximum of 700 v and 1.0 a. proper device voltage snubbing and heatsinking are required for reliable operation. a leading edge blanking circuit was placed in the current sensing signal path. this circuit prevents a premature reset of the pwm latch. the premature reset is generated each time the power switch is driven into conduction. it appears as a narrow voltage spike across the current sense resistor, and is due to the mosfet gate to source capacitance, transformer interwinding capacitance, and output rectifier recovery time. the leading edge blanking circuit has a dynamic behavior in that it masks the current signal until the power switch turn ? on transition is completed. the current limit propagation delay time is typically 300 ns. this time is measured from when an overcurrent appears at the power switch drain, to the beginning of turn ? off. error amplifier an fully compensated error amplifier with access to the inverting input and output is provided for primary side voltage sensing, figure 19. it features a typical dc voltage gain of 82 db, and a unity gain bandwidth of 1.0 mhz with 78 degrees of phase margin, figure 6. the noninverting input is internally biased at 2.6 v 3.1% and is not pinned out. the error amplifier output is pinned out for external loop compensation and as a means for directly driving the pwm comparator. the output was designed with a limited sink current capability of 270 a, allowing it to be easily overridden with a pull ? up resistor. this is desirable in applications that require secondary side voltage sensing, figure 22. in this application, the v oltage feedback input is connected to the regulator output. this disables the error amplifier by placing its output into the sink state, allowing the optocoupler transistor to directly control the pwm comparator. overvoltage protection an overvoltage protection comparator is included to eliminate the possibility of runaway output voltage. this condition can occur if the control loop feedback signal path is broken due to an external component or connection failure. the comparator is normally used to monitor the primary side v cc voltage. when the 2.6 v threshold is exceeded, it will immediately turn off the power switch, and protect the load from a severe overvoltage condition. this input can also be driven from external circuitry to inhibit converter operation. undervoltage lockout an undervoltage lockout (uvlo) comparator has been incorporated to guarantee that the integrated circuit has sufficient voltage to be fully functional before the output stage is enabled. the uvlo comparator monitors the v cc voltage at pin 3 and when it exceeds 14.5 v, the reset signal is removed from the pwm latch allowing operation of the power switch. to prevent erratic switching as the threshold is crossed, 5.0 v of hysteresis is provided. startup control an internal startup control circuit with a high voltage enhancement mode mosfet is included within the mc33363a. this circuitry allows for increased converter efficiency by eliminating the external startup resistor, and its associated power dissipation, commonly used in most off ? line converters that utilize a uc3842 type of controller. rectified ac line voltage is applied to the startup input, pin 1. this causes the mosfet to enhance and supply internal bias as well as charge current to the v cc bypass capacitor that connects from pin 3 to ground. when v cc reaches the uvlo upper threshold of 15.2 v, the ic commences operation and the startup mosfet is turned off. operating bias is now derived from the auxiliary transformer winding, and all of the device power is efficiently converted down from the rectified ac line. regulator a low current 6.5 v regulated output is available for biasing the error amplifier and any additional control system circuitry. it is capable of up to 10 ma and has short ? circuit protection. this output requires an external bypass capacitor of at least 1.0 f for stability. thermal shutdown and package internal thermal circuitry is provided to protect the power switch in the event that the maximum junction temperature is exceeded. when activated, typically at 155 c, the latch is forced into a ?reset? state, disabling the power switch. the latch is allowed to ?set? when the power switch temperature falls below 145 c. this feature is provided to prevent catastrophic failures from accidental device overheating. it is not intended to be used as a substitute for proper heatsinking. the mc33363a is contained in a heatsinkable plastic dual ? in ? line package in which the die is mounted on a special heat tab copper alloy lead frame. this tab consists of the four center ground pins that are specifically designed to improve thermal conduction from the die to the circuit board. figures 17 and 18 show a simple and effective method of utilizing the printed circuit board medium as a heat dissipater by soldering these pins to an adequate area of copper foil. this permits the use of standard layout and mounting practices while having the ability to halve the junction to air thermal resistance. the examples are for a symmetrical layout on a single ? sided board with two ounce per square foot of copper. figure 23 shows a practical example of a printed circuit board layout that utilizes the copper foil as a heat dissipater. note that a jumper was added to the layout from pins 8 to 10 in order to enhance the copper area near the device for improved thermal conductivity. the application circuit requires two ounce copper foil in order to obtain 8.0 w of continuous output power at room temperature.
mc33363a http://onsemi.com 11 figure 22. 15 w off ? line converter osc pwm pwm latch thermal ea startup reg uvlo 14.5 v/ 9.5 v ovp 2.6 v 2.6 v r1 8 6 7 4, 5, 12, 13 11 16 9 10 1 92 to 276 5.05 v/3.0 a r s q driver 3 leb mirror 270 a 13 k vac input c3 1200 pf c4 1.0 r2 2.7 k ic1 mc33363a 5 4 r4 5.1 k r3 1.0 k c2 10 c1 47 c6 47 pf c5 4.0 nf r6 180 k 1.0 w dc output c12 1.0 c11 220 r8 220 r9 2.80 k c7 100 nf 1 2 3 1 2 r10 2.74 k ic3 tl431b c8 330 c9 330 c10 330 t1 d6 mur 120 r5 39 d5 mur 1100e l1 5.0 h r7 2.2 k 1.0 w ic2 moc 8103 1n4006 d3 d4 d2 d1 f1 1.0 a i limit d7 mbr 1635 ? + table 1. converter test data test conditions results line regulation v in = 92 vac to 276 vac, i o 3.0 a = 1.0 mv load regulation v in = 115 vac, i o = 0.75 a to 3.0 a = 5.0 mv v in = 230 vac, i o = 0.75 a to 3.0 a = 5.0 mv output ripple v in = 115 vac, i o = 3.0 a triangular = 2.0 mvpp, spike = 32 mvpp v in = 230 vac, i o = 3.0 a triangular = 2.0 mvpp, spike = 34 mvpp efficiency v in = 115 vac, i o = 3.0 a 76.8%* v in = 230 vac, i o = 3.0 a 76.8% this data was taken with the components listed below mounted on the printed circuit board shown in figure 23. *with mbr2535ctl, 78.8% efficiency. pcb layout modification is required to use this rectifier. for high efficiency and small circuit board size, the sanyo os ? con capacitors are recommended for c8, c9, c10 and c11. c8, c9, c10 = sanyo os ? con #6sa330m, 330 f 6.3 v. c11 = sanyo os ? con #10sa220m, 220 f 10 v. l1 = coilcraft s5088 ? a, 5.0 h, 0.11 . t1 = coilcraft u6875 ? a primary: 77 turns of # 28 awg, pin 1 = start, pin 8 = finish. two layers 0.002 mylar tape. secondary: 5 turns of # 22 awg, 2 strands bifiliar wound, pin 5 = start, pin 4 = finish. two layers 0.002 mylar tape. auxiliary: 13 turns of # 28 awg wound in center of bobbin, pin 2 = start, pin 7 = finish. two layers 0.002 mylar tape. gap: 0.011 total for a primary inductance (l p ) of 620 h. core and bobbin: coilcraft pt1950, e187, 3f3 material.
mc33363a http://onsemi.com 12 figure 23. printed circuit board and component layout (circuit of figure 22) mc33363a (top view) (bottom view) 2.25 2.75" caution! high voltages d1 d2 f1 t1 c1 r6 c5 c6 d6 ic2 d4 d3 ac line input r4 r1 r2 j1 r3 c9 c10 ic3 dc output c4 r8 l1 d7 c3 c7 r10 c8 r9 c11 r7 d5 c2 r3 ic1 c12 r5 1
mc33363a http://onsemi.com 13 package dimensions pdip ? 16 p suffix case 648e ? 01 issue o notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension a and b does not include mold protrusion. 5. mold flash or protrusions shall not exceed 0.25 (0.010). 6. rounded corner optional. ? a ? ? b ? 16 9 18 d g h s c 13 pl s b m 0.25 (0.010) t ? t ? seating plane j m l r p f k s a dim min max min max millimeters inches a 0.740 0.760 18.80 19.30 b 0.245 0.260 6.23 6.60 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.050 0.070 1.27 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.120 0.140 3.05 3.55 l 0.295 0.305 7.50 7.74 m 0 10 0 10 p 0.200 bsc 5.08 bsc r 0.300 bsc 7.62 bsc s 0.015 0.035 0.39 0.88 so ? 16w dw suffix case 751n ? 01 issue o dim min max min max inches millimeters a 10.15 10.45 0.400 0.411 b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.50 0.90 0.020 0.035 g 1.27 bsc 0.050 bsc j 0.25 0.32 0.010 0.012 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 10.05 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029 m b m 0.010 (0.25) notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. ? a ? ? b ? p g 9x d 13x seating plane ? t ? s a m 0.010 (0.25) b s t 16 9 8 1 f j r x 45 m t s s 2.54 bsc 0.100 bsc t 3.81 bsc 0.150 bsc c k
mc33363a http://onsemi.com 14 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. mc33363a/d the product described herein (mc33363a), may be covered by one or more of the following u.s. patents: 5,418,410; 5,477,175. the re may be other patents pending. sensefet is a trademark of semiconductor components industries, llc (scillc) publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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